All Projects

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Competition 2023
Competition: Collaboration/Education
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https://www.istockphoto.com/photos/hell-fire

Hell Fire SoC

Systolic arrays are critical in parallel computing. They efficiently accomplish tasks like matrix multiplication and signal processing by coordinating a grid of processing components to perform synchronized operations. The structured data flow reduces memory access while increasing processing, resulting in substantial speedups. Systolic arrays are used in a variety of domains, from AI model training to scientific simulations, to improve speed and enable complicated computations that typical sequential approaches struggle with.

Competition 2023
Competition: Collaboration/Education
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Fast-kNN: A hardware implementation of a k-Nearest-Neighbours classifier for accelerated inference
Project Motivation and Goals

The k-Nearest-Neighbours (kNN) algorithm is a popular Machine Learning technique that can be used for a variety of supervised classification tasks. In contrast to other machine learning algorithms which "encode" the knowledge gained from training data to a set of parameters, such as weights and biases, the parameter set of a kNN classifier consists of just labelled training examples. Classification of an unlabelled example takes place by calculating its Euclidean distance (or any other type of distance metric) from all the stored training examples.

Reference Design
Case Study
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dwn @ soclabs

nanosoc re-usable MCU platform
A small Arm Cortex-M0-based SoC development framework to support research demonstrator designs. Successfully used for 2023/4 competition tape-outs, now archived as a Case Study
Collaborative
Case Study
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dwf @soton.ac.uk

Building system-optimised AMBA interconnect
Example case-study of using the Arm CMSDK AMBA-AHB Bus-Matrix tools to build system-optimised interconnect.
Collaborative
Active Project
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SHA-2 Accelerator Engine

Motivation

At SoC Labs, we have need of an accelerator to test our SoC infrastructure and confirmation of our accelerator wrapper design to get size and performance information as well as to try and get ahead and uncover potential problems researchers may experience trying to put their IP into the reference SoC.

 

Specification

The preliminary design has been broken into two main blocks:

Collaborative
Case Study
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DMA Infrastructure Developments
The aim of of this project is to produce a variety of DMA Infrastructures for reusable SoC reference designs containing Arm-based microprocessors that can be picked up and used by researchers, academics and students with minimal modifications to allow them to easily implement experimental systems.
Collaborative
Case Study
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Efficient Keyword-Spotting on an Arm M7 microcontroller
This 4 month PhD Interdisciplinary Team Project used an Arm M7 to measure actual energy used in different forms of inference and feature extraction for keyword spotting.
Collaborative
Active Project
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dflynn-University of Southampton

Arm Cortex-M0 microcontroller
A reference design based on an Arm Cortex-M0 CPU and the Cortex-M0 Design Kit provided in the Corstone-101 subsystem package, available under the Arm Academic Access agreement.
Collaborative
Active Project
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Fused: Closed-loop Performance and Energy Simulation of Embedded Systems

Fused is a full-system simulator for modelling energy-driven computers. To accurately model the interplay between energy-availability, power consumption, and execution; Fused models energy and execution in a closed feedback loop.

Collaborative
Active Project
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d.wf @ soclabs

Hardware SoC bus level debug agent (v4)
A hardware Finite State Machine on-chip AMBA interconnect controller using a serial ASCII debug protocol, with functional upgrades to Version 4 to support 8-, 16- and 32-bit accesses, to facilitate off-chip validation.