Synthesis

Is the process step to transform the technology independent register-transfer level (RTL) description of a system into a technology dependent netlist using a specific technology cell library.

Most Electronic Design Automation Synthesis tools support translation from designs written in SystemVerilog, Verilog, VHDL or a mixture of them. 

Synthesis can be defined to optimise the output for different criteria, for example area use, timing, allowable loads on signals, the movement or merging of registers, or to control the amount of time a synthesis takes. Synthesis attributes and directives can be included in the source, for example to direct the synthesis to perform or not certain actions when synthesizing a design. Synthesis Attributes, such as expected arrival time of a signal at an input port, and Constraints, such as maximum input to output delay, are added to direct the synthesis.

Synthesis can be initiated from within an Integrated Design Environment by the designer or via a command interface that can be used to make scripts and automation of the process.

Cadence - Genus

This step takes our verilog modules, and a liberty standard cell library and turns it into a netlist. A netlist is a functionally equivalent file to the verilog file but uses explicit declarations of cells, and the connections between them.

In Genus, the steps for synthesis are

• Load library files
• Read in verilog/HDL and elaborate design
• Read in constraints
• Synthesize to generic gates (i.e. not technology specific)
• Map gates to technology gates
• Optimisize netlist using constraints against the netlist
• Write reports on timing, power, area etc.
• Save and export netlist (Plus UPF, LEC files, and DFT files if needed)

An example script for genus synthesis can be found in our git repository