All Projects

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Collaborative
Active Project
PTP Hardware Clock: Sub-Nanosecond Timekeeping for Chiplet Systems
Introduction

Precision timekeeping is a foundational service in any distributed system. Whether synchronising Ethernet frames to a PTP grandmaster, timestamping die-to-die packet exchanges between chiplets, or scheduling time-critical hardware events, the system needs a clock that is accurate, capturable at multiple points simultaneously, and adjustable by both hardware servo loops and software without stopping.

Collaborative
Active Project
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NanoSoC Ethernet Subsystem
The NanoSoC Ethernet Subsystem provides an AHB based TCP/IP Offload Engine that provides a SoC system with external Ethernet connectivity without adding the network handling workload to the main SoC processor.
Collaborative
Active Project
AHB Chiplet Communication
To utilise chiplets for small M-class microcontroller based systems there is a need to extend the range of the AHB standard on-chip bus interconnect. This 'Tidelink' project extends the planned AXI Chiplet controller to support AHB transactions across chiplets.
Collaborative
Active Project
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Implementing a UDP Echo Server using XIlinx Microblaze on a Pynq-Z2 with LAN8720 Ethernet PHY Board
This project demonstrates running the lwIP UDP/IP stack on a MicroBlaze soft processor within an XIlinx PYNQ-Z2 FPGA to create a simple embedded Ethernet communications subsystem. The design integrates a custom Ethernet PHY interface and AXI EthernetLite MAC to enable basic networking functionality. An lwIP echo server runs on the MicroBlaze, while the Zynq Processing System hosts a UART bridge application for host communication. The project is being used to undertake design exploration for soft-core processors in FPGA logic to implement and verify lightweight networking stacks.
Reference Design
Active Project
nanoSoC V3, the next version of nanoSoC
This project aims to access the user needs and develop the next increment of capability for nanoSoC. It outlines the justification and motives behind the architectural redesign, design flow improvements and code repository refactor. With a number of new subsystems planned for nanoSoC and learning from various projects to date, this version of nanoSOC is expected to provide a much better support for academic projects.
Reference Design
Active Project
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AXI Chiplet Controller Architecture
dwn @ soclabs

AXI Chiplet Controller

For a chiplet system, you need a communication interface between chiplets. The industry has developed standards that require complicated IPs around UCIe and the CHI interface from Arm. For many academic projects these are probably more complicated than needed . The aim of this project is to produce a simple chiplet communications interface based around the open standard AXI protocol. 

The project is hosted here: https://git.soton.ac.uk/soclabs/chiplets/axi-chiplet-controller

Competition 2025
Competition: Hardware Implementation
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ASIC for parallel channel tuning on Reconfigurable Intelligent Surfaces

Reconfigurable Intelligent Surfaces (RIS) are planar structures composed of large arrays of tunable elements that can dynamically redirect, reflect, or shape wireless signals in the environment.

Reference Design
Active Project
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PCK600 to SIE300 subsytem
dwn @ soclabs

PCK600 Integration in megaSoC

The PCK600 Arm IP provides components to allow a power control infrastructure to be distributed in a SoC in order to make a design energy efficient. Arm provide the IP as part of their Power Control System Architecture that can be used to control the power states of various parts of the system. This control of the power infrastructure is achieved through the use of the Power Policy Unit (PPU). This unit has an APB interface to allow for software control, and some low power interfaces that can connect to the power controllable IP within the system.

Competition 2025
Competition: Collaboration/Education
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RF-Powered Sensor Platform for Intelligent Groceries Transportation Monitoring

This project aims to develop an advanced RF energy harvesting (EH) receiver chip specifically designed to power embedded sensors for monitoring the condition of groceries during transportation. The receiver chip captures wireless energy transmitted from phased array antennas and converts it into electrical power that is used to operate onboard sensors, which continuously monitor critical parameters such as temperature and humidity inside delivery trucks.

Competition 2025
Competition: Hardware Implementation
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Neural Activity Processor

Stroke and epilepsy are among the most common debilitating neurological conditions, with a worldwide prevalence of 100 million people (World Stroke Organization, 2022) and 50 million people (World Health Organization, 2024), respectively. Present-day approaches for treating neurological and neurosurgical conditions include physiotherapy, pharmacological treatment, surgical excision, and interventions such as deep brain stimulation.