As part of plans for continued development of nanoSoC one area that requires improvement is the power structure of system. The first iteration of nanoSoC contained 2 power domains: the accelerator domain and the remainder of the SoC. Both power domains were connected to external pins to allow connection to separate external voltage regulators and power measurement ICs, as implemented in the first version of the nanoSoC testboard.

There is growing interest within the SoC Labs community for an Arm A-Class SoC that can support a full operating system, undertake more complex compute tasks and enable more complicated software directed research. The Cortex-A53 is Arm's most widely deployed 64-bit Armv8-A processor and can provide these capabilities with power efficiency. 

This project aims to design and implement a high capacity memory subsystem for Arm A series processor based SoC designs.  The current focus of the project is the design and implementation of a Memory Controller for DDR4 memory. 

The Synopsys HAPS® System adds additional capabilities to the FPGA-based prototyping environments SoC Labs can use to support projects. The HAPS® system provides a greater amount of logic resources supporting development of larger SoC designs. It can be used to support multiple projects simultaneously. It is used by many semiconductor companies, including arm for their CPU verification. This collaboration project will use the HAPS® system in SoC Labs projects and share with the community experience in utilising such systems.

This collaboration project is aimed at providing specific tailored activities to the local geography in Canada by developing local actions that will help stimulate academics and their institutions and the broader semiconductor industry supporters to create new and exciting SoC design projects. 

It may include holding specific local physical meetups where people can exchange design ideas.

It may include utilising locally provided routes to fabrication.

It may include sharing hard to locate test capability across academic institutions.

On-chip SRAM in ASICs can use a significant area, which equates to a significant cost. One solution is to make the memory off-chip. This project explores the use of Arm IP to create an SRAM chiplet design. The benefit  is that standard memory chiplets can be fabricated at lower cost and used across multiple projects, miminising silicon area to the unique project needs.

Project Overview:

Our innovative SoC design for precision agriculture revolutionizes field management by deploying a robust mesh network of sensor-based devices, capable of detailed monitoring and swift response to variations in soil health, erosion, drought, and pest activities. This system not only ensures reliability through its mesh architecture—eliminating single points of failure—but also incorporates diverse sensors for comprehensive data acquisition. It's engineered for energy efficiency to sustain operation throughout an entire crop season, significantly optimizing resource use and reducing waste.

The aim of this project is to define a mixed signal subsystem for the nanosoc reference design. 

The mixed signal subsystem should be able to sample analog signals at a regular sampling rate, and transmit a digital representation of this signal to the rest of the nanosoc system. In order to interface with real-world signals in a digital System on Chip ("SoC"), an analog to digital conversion ("ADC") is needed. 

This project focuses on developing a plant growth monitoring system for space exploration missions using the ARM Cortex-M0 microcontroller core. The projects aim to develop a SOC based on ARM M0 core for interactive plant monitoring by interfacing AHB lite, GPIO, timers, and communication protocols such as UART, I2C, SPI, and co-processors.  This project also proposes two co-processors for interactive plant monitoring and control. One AI co-processor for classification and prediction of plant and environmental data.