The NanoSoC Ethernet Subsystem provides an AHB based TCP/IP Offload Engine that provides a SoC system with external Ethernet connectivity without adding the network handling workload to the main SoC processor.

To utilise chiplets for small M-class microcontroller based systems there is a need to extend the range of the AHB standard on-chip bus interconnect. This 'Tidelink' project extends the planned AXI Chiplet controller to support AHB transactions across chiplets.

This project demonstrates running the lwIP UDP/IP stack on a MicroBlaze soft processor within an XIlinx PYNQ-Z2 FPGA to create a simple embedded Ethernet communications subsystem. The design integrates a custom Ethernet PHY interface and AXI EthernetLite MAC to enable basic networking functionality. An lwIP echo server runs on the MicroBlaze, while the Zynq Processing System hosts a UART bridge application for host communication. The project is being used to undertake design exploration for soft-core processors in FPGA logic to implement and verify lightweight networking stacks.

This project aims to access the user needs and develop the next increment of capability for nanoSoC. It outlines the justification and motives behind the architectural redesign, design flow improvements and code repository refactor. With a number of new subsystems planned for nanoSoC and learning from various projects to date, this version of nanoSOC is expected to provide a much better support for academic projects.