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Profile picture for user AlexW
Name
Dr Alex Weddell
Research Area
energy harvesting systems, IoT
Role
Lecturer
Profile picture for user dwflynn
Name
David Flynn
Research Area
Low power system design
Role
Consultant
Placeholder
Name
Lance Draper
Research Area
Physical and Applied Sciences
Role
Research Systems Manager
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Name
Geoff Merrett
Research Area
energy-efficient computing
Role
Professor
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Name
Samuel
Research Area
Intermittent Computing, Energy-aware design
Role
Student
Profile picture for user arezou.nayebi
Name
Arezou Nayebi
Research Area
Machine Intelligence for Nano-Electronic Devices and Systems, Secure and Resilient Hardware Implementation of AI Modules
Role
Postgraduate researcher
Profile picture for user Shafi R
Name
Shafiullah Rahman
Research Area
Machine Intelligence for Nano-Electronic Devices and Systems | Reinforcement Learning
Role
Postgraduate Researcher

University of Southampton

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United Kingdom of Great Britain and Northern Ireland (the)
Members icon Members 37
Projects icon Projects 33
Articles icon Articles 7
Contributor since icon Contributor since: Wed, 06/30/2021 - 14:50
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Projects

Reference Design
Active Project
nanoSoC V3, the next version of nanoSoC
This project aims to access the user needs and develop the next increment of capability for nanoSoC. It outlines the justification and motives behind the architectural redesign, design flow improvements and code repository refactor. With a number of new subsystems planned for nanoSoC and learning from various projects to date, this version of nanoSOC is expected to provide a much better support for academic projects.

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Reference Design
Active Project
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AXI Chiplet Controller Architecture
dwn @ soclabs

AXI Chiplet Controller

For a chiplet system, you need a communication interface between chiplets. The industry has developed standards that require complicated IPs around UCIe and the CHI interface from Arm. For many academic projects these are probably more complicated than needed . The aim of this project is to produce a simple chiplet communications interface based around the open standard AXI protocol. 

The project is hosted here: https://git.soton.ac.uk/soclabs/chiplets/axi-chiplet-controller


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Competition 2025
Competition: Hardware Implementation
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ASIC for parallel channel tuning on Reconfigurable Intelligent Surfaces

Reconfigurable Intelligent Surfaces (RIS) are planar structures composed of large arrays of tunable elements that can dynamically redirect, reflect, or shape wireless signals in the environment.


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Reference Design
Active Project
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PCK600 to SIE300 subsytem
dwn @ soclabs

PCK600 Integration in megaSoC

The PCK600 Arm IP provides components to allow a power control infrastructure to be distributed in a SoC in order to make a design energy efficient. Arm provide the IP as part of their Power Control System Architecture that can be used to control the power states of various parts of the system. This control of the power infrastructure is achieved through the use of the Power Policy Unit (PPU). This unit has an APB interface to allow for software control, and some low power interfaces that can connect to the power controllable IP within the system.


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