Hi,

Thank you for submitting this project it looks very interesting. I noticed in your IEEE paper that the M3 had 32Kb Data and Instruction caches. There were also two DMA engines? and 4 additional 32 Kb SRAM blocks. There was no description of these in the paper.  Which DMA engines did you use, were these Arm IP?

We use both the DMA PL230 and DMA 350 Arm IP in the nanoSoC reference design.

We look forward to hearing from you.

John.