
Aspen: A 630 FPS Real-Time Posit-Based Unified Accelerator for Extended Reality Perception Workloads
Aspen is a unified accelerator for deep neural network (DNN)-based extended reality perception workloads. Aspen proposes a mixed-precision quantization scheme using the posit datatype to reduce memory usage while maintaining accuracy, a DNN accelerator for mixed-precision posit datatypes, and efficient data prefetching and data layout to minimize data reorganization. The Aspen system-on-chip has an Arm Cortex-M3 CPU, a mixed-precision posit-based DNN accelerator, and 4 megabytes of SRAM partitioned into eight 512 KB banks, connected through a 128-bit-wide interconnect. The DNN accelerator consists of a matrix unit and a vector unit. Aspen is fabricated in Intel 16 and achieves real-time processing of visual inertial odometry, eye gaze extraction, and object classification at 98.9, 630, and 31 frames per second, respectively.
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Aspen: Accelerator for Extended Reality Perception
Hi,
Thank you for submitting this project it looks very interesting. I noticed in your IEEE paper that the M3 had 32Kb Data and Instruction caches. There were also two DMA engines? and 4 additional 32 Kb SRAM blocks. There was no description of these in the paper. Which DMA engines did you use, were these Arm IP?
We use both the DMA PL230 and DMA 350 Arm IP in the nanoSoC reference design.
We look forward to hearing from you.
John.
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