Dear Prof. Darlington,

Thank you very much for the message.

We are interested in building SoC platform for doing research in Vietnam Nation University, Hanoi in particular, and supporting Vietnamese community in general. 

My students are starting to create projects and work on them.

Best regards,

Duy-Hieu Bui

Hello,

I am trying to run the example project; however, when I tried to generate the IPs, I got this errror massages from the DMA:

Top-level rendered RTL:
- /home/admin/projects/megasoc_project/megasoc_tech/logical/CortexA53_1/verilog/CORTEXA53.v
Configuring component 'sie300_axi5_sram_ctrl' with config '1'...
SIE-300 render completed successfully
Configuring component 'sie300_axi5_sram_ctrl' with config 'sys'...
SIE-300 render completed successfully
%info   build_ip        No value specified for parameter CH_4_FIFO_DEPTH using default 2
%info   build_ip        No value specified for parameter CH_5_FIFO_DEPTH using default 2
%info   build_ip        No value specified for parameter CH_6_FIFO_DEPTH using default 2
%info   build_ip        No value specified for parameter CH_7_FIFO_DEPTH using default 2
%info   generate        Configuration validation passed
%info   build_ip        No value specified for parameter CH_4_FIFO_DEPTH using default 2
%info   build_ip        No value specified for parameter CH_5_FIFO_DEPTH using default 2
%info   build_ip        No value specified for parameter CH_6_FIFO_DEPTH using default 2
%info   build_ip        No value specified for parameter CH_7_FIFO_DEPTH using default 2
%error  render  Could not open /home/dkits/arm/CG096/CG096-BU-50000-r0p0-00rel0/dma350/logical/models/modules/generic/address_map_m1_megasoc.sv template for rendering
%error  build_ip        rendering failed
make: *** [makefile:26: build_dma350] Error 1

It seems that the address_map_m1_megasoc.sv is missing in the source tree.

Would you please help to solve this issue?

Thank you very much.

Hi Daniel,

Thank you very much for the quick response.

I still got an error because the expansion_subsystem_tech directory is missing.

This is the output of 'make compile' command:

Error-[SFCOR] Source file cannot be opened
 Source file
 "/home/admin/projects/megasoc_project/expansion_subsystem_tech/logical/top_expansion_subsystem/verilog/expansion_subsystem_wrapper.v"
 cannot be opened for reading due to 'No such file or directory'.
 Please fix above issue and compile again.

I tried to change the variable SOCLABS_MEGASOC_EXP_TECH_DIR into $SOCLABS_PROJECT_DIR/megasoc_tech by modifying the makefile

export SOCLABS_MEGASOC_EXP_TECH_DIR="$SOCLABS_PROJECT_DIR/megasoc_tech"

but some files are still missing:

Error-[SFCOR] Source file cannot be opened
 Source file
 "/home/admin/projects/megasoc_project/expansion_subsystem_tech/logical/SRAM/verilog/EXP_SRAM_wrapper.v"
 cannot be opened for reading due to 'No such file or directory'.
 Please fix above issue and compile again.

In addition, the variable 'CORTEX_A53_IP_LOGICAL_DIR' is set to /research/AAA/ip_library/Cortex-A53/MP030-r0p4-52rel2/MP030-BU-50000-r0p4-52rel2/cortexa53/logical by default. I think it is better to set it to '$(ARM_IP_LIBRARY_PATH)/Cortex-A53/MP030-r0p4-52rel2/MP030-BU-50000-r0p4-52rel2/cortexa53/logical' which can be customized based on the ARM_IP_LIBRARY_PATH.

Duy Hieu