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Kanishka De
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Low Power ASIC Design
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Low power design

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Thanks John.  My expertise…

Thanks John.  My expertise and interest are primarily on the low power design side (power control system architecture, clock/power gating/ reset design/DVFS control etc) and I am looking to be involved in the architecture and RTL design stage.  But I understand that they heavily use ARM components. Let me know If some related projected opens up in the future (if not an exact match to my interest/expertise) 

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Hi,

I am very sorry for missing the message you sent to us. You don't have to be a student at an academic organisation to collaborate on a project but under the Arm AAA agreement you will not be able to access any Arm IP. It would be good to understand what you want to acheive and see if we can connect you to a project. There is a project on memory controller that is open to non-academics.

High Capacity Memory Subsystem Development | SoC Labs

John.

 

Thanks John.  My expertise and interest are primarily on the low power design side (power control system architecture, clock/power gating/ reset design/DVFS control etc) and I am looking to be involved in the architecture and RTL design stage.  But I understand that they heavily use ARM components. Let me know If some related projected opens up in the future (if not an exact match to my interest/expertise) 

Hi,

I see you signed up for the Interest on Low Power Design. I am keen to get people to help add interesting content to this area of Interest. I have added a comment to encourage people but will repeat it here:

It is easy to do. Just click on the Edit tab when logged in.

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Once you are happy with your submission. Save to Editorial review.

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You can also simple add a comment that is also a good way to add information of interest.

We look forward to hearing from you.

Hi,

Please do consider adding some content from you experience. We are trying to describe the various stages of design in our design flows section. Let's take Architectural Design stage and say Specifying a SoC. How would you go about deciding how to partition an SoC from a power control point of view. You can either write this up in the Low power design interest page or by adding paragraphs to the various design flow stages that are impacted by low power design activities.

We look forward to hearing from you.

John.

 

 

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