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Hi Rami,

We've just updated the way you can configure nanosoc, to hopefully make it more easy for people to make changes to the overall configuration without having to change multiple files. If you pull the latest changes you should see a nanosoc.config in the nanosoc_tech directory

If you leave the options blank, they will not be included and if you write a yes (or really any text after) then it will be included. There is also a section to edit the paths to arm IP

You should now not have to make any edits to flists (apart from to include your accelerator) or to any of the makefiles

Let me know how it goes

Daniel

Hi,

We've just updated the nanosoc accelerator project repository, there is now a new way to configure nanosoc including how to include the ADC's.

If you go into the nanosoc_tech directory there is a file nanosoc.config. If you add text after any of the ADC_x_INCLUDE =  then the APB bus will be configured for an ADC, and the verilog-ams model of the ADC will be included (this is not synthesizable for FPGA or ASIC - we're working on making this available soon). There is also a test for the adc subsystem called adc_tests. This can be run from the nanosoc_tech directory with 

make run_vcs TESTNAME=adc_tests

Unfortunately at the moment, synopsys VCS is the only supported simulator for the ADC, but we are working on this

Daniel

Hi,

We've just updated the nanosoc accelerator project repository, there is now a new way to configure nanosoc including how to include the ADC's.

If you go into the nanosoc_tech directory there is a file nanosoc.config. If you add text after any of the ADC_x_INCLUDE =  then the APB bus will be configured for an ADC, and the verilog-ams model of the ADC will be included (this is not synthesizable for FPGA or ASIC - we're working on making this available soon). There is also a test for the adc subsystem called adc_tests. This can be run from the nanosoc_tech directory with 

make run_vcs TESTNAME=adc_tests

Unfortunately at the moment, synopsys VCS is the only supported simulator for the ADC, but we are working on this

Daniel

Hi,

Not sure if you have seen, but the team from Sydney have just posted their project for the competition and it shares some similar elements to what you are trying to achieve. If you want to check it out, its here:  https://soclabs.org/project/sensing-precision-agriculture 

Just to add to this, Europractice don't support a 90nm mini ASIC tapeout. 
As reference we have recently taped out some dies with nanoSoC using TSMC's 65nm mini ASIC shuttles with a 1 x 1.5 mm size so this may be a better technology node to target, but happy to discuss this with you further

Hi, 
Just to add to this, if you clone the accelerator project repository (have to use recursive clone to get all the submodules) you will find that there are commands to run with Quickstart (similar to design start that you do not get the DMA PL230 or DMA-350) The only IP you need for this is the Cortex M0 and CMSDK / Corstone-101
For simulations or building the FPGA image you just have to add the QUICKSTART=yes to any command that you run from command line. This will then simulate/build a version of nanosoc without the DMA's included

Daniel

Hi, 
We currently have published a verilog-ams model of the ADC here 
We still need to figure out exactly how we are supposed to share the full macro for backend analysis without breaking NDA with TSMC. But I will keep you updated on that.
This block has been integrated in nanosoc, you just have to make changes to the nanosoc.config file and set ADC_0_INCLUDE:=yes to include the ADC subsystem. This currently works well with VCS simulator, I've not completely figured out yet how to support verilog-AMS code on other simulators 

Hi, 

1. You should be able to quite easily integrate your AXI accelerator within one of our Soc reference designs. They have memory mapped ports specifically for an accelerator to be added 
2. This really depends on your accelerator requirements, in particular data rate and size. What we have available and are currently working on is outlined below
   1. nanoSoC (proven in silicon): microcontroller SoC with Cortex M0 and AHB lite interconnect. For data rates <5 Gbps (on chip) and 50 Mbps (off chip), total on chip SRAM ~64KB. Max Clock speed  240 MHz (on TSMC 65nm)
   2. milliSoC (under development): Real time SoC with Cortex R5 and AXI interconnect. For data rates ~25 Gbps (on chip) and ~200 Mbps (off chip), total SRAM ~ 512KB. Max clock speed ~400 MHz (assuming TSMC 28nm)
   3. megaSoC (under development): Compute SoC with Cortex A53 and AXI interconnect. For data rates ~50-100 Gbps (on chip) and ~1 Gbps (off chip) total SRAM >2MB. Max clock ~0.8-1 GHz (assuming TSMC 16nm)
3. Minimal modification would be needed to your accelerator however testcode will need to be ported to the SoC architecture. We can also advise on any modification that you may want to make for ASIC implementation. This is also assuming that you haven't used any FPGA macros in your design that would have to be replaced for an ASIC flow
4. Possibly already answered in 2, but in terms of power and performance it will go roughly like:
   1. nanoSoC: low power - lower performance
   2. milliSoC: medium power -medium performance
   3. megaSoC: higher power - high performance
   4. That being said, the power/performance of your accelerator can be different to the SoC and may be more linked to the process node that you chose
5. We try to make this easily transferable from FPGA to ASIC. However, the ASICs will be running C/C++/assembly. We are planning to enable megaSoC to run a full Linux OS in which you could use python, but nanoSoC is a bare-metal microcontroller and milliSoC will probably be running an RTOS (such as FreeRTOS). So answer is really it depends how much you rely on python as a language and if it's easy to translate to C.
6. Again probably minimal modification but without seeing the design of your accelerator it is difficult to say

Each of our reference SoC's are at different development stages, so this will also depend on your timeline. If you want something ready to go very quickly I would suggest looking into nanoSoC

Hi All, 
Could you please use this link to join the introductory meeting this friday at 3pm UK time (BST)
https://teams.microsoft.com/l/meetup-join/19%3ameeting_NzJmOWMzZjQtMTYxNi00NTA3LTlhMTQtMjMwNDY4N2NhMDQw%40thread.v2/0?context=%7b%22Tid%22%3a%224a5378f9-29f4-4d3e-be89-669d03ada9d8%22%2c%22Oid%22%3a%22da03259c-2f3e-4038-96bb-de5e01994a6c%22%7d