It would be good to understand what you are working on and what you are interested in collaborating on with SoC Labs. If you can tell us something about your interests that would be great.

We look forward to hearing from you.

John.

Thank you for the message and for the opportunity to connect. I am a pre-final year undergraduate student at IIT Kharagpur, pursuing an Integrated B.Tech–M.Tech in Electronics and Electrical Communication Engineering. My academic and research interests lie in computer architecture, system design, and memory systems, basically anything that involves hardware at the architectural and micro-architectural level.

Some of my recent and ongoing work includes:

1. Metro-MPI Project (GSoC 2025, FOSSi Foundation): I have just finished my first open-source project, in which I developed a compile-time RTL partitioning and MPI-based scheduling framework within Verilator, tested on OpenPiton (a manycore NoC-based RISC-V processor), to optimize large-scale hardware simulations. Project link
2. Hardware Security Research: Worked on few hardware security projects, leading to these Publications .
3. Speculative Execution Mitigation (Bachelor Thesis - 1): Currently, I am working on a secure processor design that can solve cache-based side-channel vulnerabilities entirely in hardware. I have developed a mitigation that works, and I am implementing it in gem5. The design is ISA-agnostic, but I am currently testing it on RISC-V and x86 ISAs.

From December, I will also begin a remote research internship with the SAFARI Research Group at ETH Zurich under prof. Onur Mutlu, focusing on memory systems. 

For collaboration with SoC Labs, I am particularly keen on:

• Extending my processor design to ARM-based platforms to demonstrate its true ISA-agnostic nature. So far, I have validated my work mainly on RISC-V and x86 because resources and reference implementations are more readily available, but I would like to explore ARM-based SoCs to broaden its relevance.
• Gaining hands-on experience with ARM frameworks and tools, since most mainstream product companies rely on ARM architectures, and SoC Labs provides an excellent opportunity to bridge my prior RISC-V-focused experience with ARM ecosystems.

I would be glad to explore how I can contribute to ongoing or future SoC Labs projects while aligning them with my research interests.

Best,
Kislay