An audio classification CNN model deployed on a low-cost ARM Cortex-M0-based SoC

The goal of this project is to design and train a CNN model for spoken digit classification and deploy it on a low-cost system-on-chip (SoC) built around an ARM Cortex-M0 microcontroller with a dedicated CNN accelerator. The SoC will be deployed as a prototype on an FPGA. Its throughput, latency and energy consumption per inference, along with its FPGA resource utilisation, will then be evaluated and compared against other systems.

The nanoSoC reference design developed by SoC Labs will serve as the basis for the Cortex-M0-based SoC. A CNN model for spoken digit classification will be trained and integrated into nanoSoC. No ASIC will be developed and the system will instead be deployed on an FPGA for prototyping and demonstration purposes. The same trained CNN will be deployed on three platforms for comparison: a standalone Cortex-M0 running the network in software (the CPU baseline), nanoSoC with the custom CNN accelerator, and the deep learning processor generated by MathWorks' Deep Learning HDL Toolbox, which represents a typical FPGA CNN workflow.

This project is undertaken as part of: ESCP3000/ESCP3001 Part III Individual Project at the University of Southampton

Project Supervisor: Mark Zwolinski

Comments

Getting you added to AAA

Hi,

I saw your request to be added to AAA.

"I am an MEng Electrical and Electronic Engineering student at the University of Southampton, and I am writing to request Arm Academic Access (AAA) membership to use the Arm Cortex-M0 IP for my individual project. My project involves implementing a CNN-based audio classification accelerator on the nanoSoC reference design, which uses the Cortex-M0 processor. My project supervisor is Professor Mark Zwolinski."

I will ask Daniel Newbrook to arrange that for you as you are based in Southampton.

That action is part of your 'Getting Started' milestone.

John.

Getting added to AAA

Thank you very much for the assistance.

Warm regards,

Melvin

Some comments in another project might help plan your project

You might want to look at some of the comments that were made in this project:

FPGA-Powered Acceleration for NLP Tasks | SoC Labs

John.

Getting Started

Hi,

Thanks for opening a SoC Labs project. We have an area of the site Design Flow where we are developing material to describe the steps necessary to take a System on Chip design from initial concept to final implementation. In your case that will be an FPGA implementation only and not a full ASIC tape out.

The first step is Getting Started

Please Edit your project and click on

Start to type getting started into the Design Flow field and it should auto populate, select.

You can edit it later and add details in the description as you complete things. Set yourself a target date for completing it. It does not matter what you guess. Part of learning about SoC design is learning to estimate how long things will take. You learn by making estimates and then realising just how long things take, you get better the more you do it.

By adding your first milestone a Project Tracker gets added to your project.